What do you mean by this? When you set it in sigmastudio, then click link-compile, you then have to export the schematic. That then is used with cygwin to make the file that is incorporated into your application in CCES.
The processor isn’t necessarily the issue, the question is whether the board only is capable of specific sample rates due to the use of specific parts that only allow for it to accurately use a specific sample rate. Many times, the crystal oscillator on the board is the same, but it is the setting of the divisor that then sets the sample rate that the crystal oscillator is keeping time for.
So I understand you may have the understanding that it will always be set at the specific rate, but I believe that is false. You are setting the sample rate in sigmastudio to later be incorporated into the LDR file generated in CCES.
Where did you get that you cannot change it in sigmastudio, if I may ask? Can you point me to the source?